In a graphical modeling environment communication of data between tasks executed with different rate characteristics is problematic. One problem that arises in a multi-rate graphical model is the communication of data between two tasks having different priorities and one or both of the tasks execute at an asynchronous rate.
FIG. 1 illustrates a multi-rate graphical model 10 having a number of tasks that execute at various asynchronous rates. The tasks contain executable code generated by the illustrated blocks. An asynchronous rate is characterized as a rate of irregular occurrence (i.e. aperiodic). The multi-rate graphical model 10 also includes a number of blocks associated with tasks that execute at discrete rates. A discrete rate is characterized as a rate that occurs, or re-occurs, at regular intervals (i.e. periodic). In the multi-rate graphical model 10, task synchronization block 30, count block 32, asynchronous rate transition block 34, and algorithm block 44, are each associated with one or more tasks that execute at one or more asynchronous rates. In contrast, first time block 20, second time block 22, division block 24, interrupt control block 28, sum block 46 and gain block 48 are each associated with tasks that execute at discrete rates.
In the multi-rate graphical model 10, count block 32 is associated with a task that executes at a first asynchronous rate. The first asynchronous rate corresponds to the assertion of a first system interrupt 26A by the interrupt modeled by control block 28. The task synchronization block 30 is associated with a task that executes at a second asynchronous rate. The second asynchronous rate corresponds to assertion of a second interrupt 26B, modeled by the interrupt control block 28. Algorithm block 44 is associated with a task that executes at a third asynchronous rate. The third asynchronous rate corresponds to an aperiodic task modeled by the task synchronization block 30 as it services the second interrupt 26B.
In a real time implementation of the multi-rate graphical model 10, the tasks executing at discrete rates are assigned priorities based on the results of a scheduling algorithm, (for example, a rate monotonic algorithm that assigns the priority of each task according to its period so that the shorter of a period the higher the priority). By contrast, count block 32, task synchronization block 30, and algorithm block 44 are each associated with tasks operating with asynchronous rate characteristics. These tasks are assigned arbitrary priorities. That is, the arbitrary priorities can have priority levels above or below the priority levels assigned to any discrete task in the multi-rate graphical model 10.
FIG. 2 illustrates a first timeline 60 illustrating execution of an exemplary asynchronous task in the multi-rate graphical model 10, assigned a low priority and a second timeline 62 illustrating execution of an exemplary discrete task in the multi-rate graphical model 10, and assigned a priority higher than the asynchronous task. For purposes of the discussion below, timeline 60 is discussed in relation to a task associated with the algorithm block 44 that executes at a third asynchronous rate and timeline 62 is discussed in relation to a task associated with the sum block 46 that executes at a discrete rate assigned a higher priority than the third asynchronous rate of the algorithm block 44. Furthermore, for the discussion of FIG. 2, data transfer between tasks that are modeled by the connection between the sum block and the algorithm block is performed through the use of a global variable to which the tasks associated with algorithm block 44 and the sum block 46 share access.
For purposes of the discussion below, the data transferred is represented by a vector with ten elements and of data type double or 80 bytes. As such, because data is transferred from the task associated with algorithm block 44 to the task associated with sum block 46 without any assurances of data integrity in the multi-rate graphical model 10, there are instances when the task associated with algorithm block 44 is in the process of updating the associated memory space when the task associated with sum block 46, having the higher priority, preempts the data write of the task associated with algorithm block 44. Consequently the preemption of the memory write operation by the task associated with the sum block 46 results in the task associated with sum block 46 reading partially updated data from the memory space, hence causing problematic results due to the use of partially updated or corrupted data.
Timelines 60 and 62 depict such a scenario. Time intervals 64 of timeline 60 represent the preemption of the asynchronous task, for example a task associated with algorithm block 44 that is preempted by a task having synchronous rate characteristics associated with sum block 46, which is represented by timeline 62. Time intervals 66 of timeline 60 represent portions of a total time period (write W1+write W2) for the task associated with algorithm block 44 to carry out a memory write operation. Time intervals 68 (R1-R9) of timeline 62 represent individual time intervals for the discrete task associated with sum block 46 to perform a read operation from memory. As depicted in timelines 60 and 62, the asynchronous task associated with algorithm block 44 is in the process writing to memory at write W1 when the synchronous task associated with sum block 46 preempts the write operation resulting in the discrete task associated with sum block 46 reading partially updated or corrupted data. Consequently the data transfer between a task having a first rate characteristic and a first priority to a task having a second rate characteristic and a second priority is problematic.
As discussed in relation to FIG. 2, the data transfer is between an asynchronous task and a synchronous task when the asynchronous task is assigned a lower priority than the synchronous task results in problematic data transfers. Nevertheless, problematic data transfers also occur in a multi-rate graphical model when the asynchronous task is assigned a priority higher than an associated synchronous task. FIG. 3 depicts timelines 70 and 72 representing a data transfer between an asynchronous task and a synchronous task when the asynchronous task is assigned a higher priority then the synchronous task. Timeline 70 represents the operation of the asynchronous task assigned a high priority relative to an assigned priority of an associated synchronous task in the multi-rate graphical model 10. Timeline 72 represents operation of the synchronous task assigned a lower priority relative to the priority assigned to an asynchronous task operating in the multi-rate graphical model 10. For purposes of the following discussion, the asynchronous task represented by timeline 70 corresponds to an asynchronous task associated with algorithm block 44 while the synchronous task represented by timeline 72 corresponds to a synchronous task associated with sum block 46.
As depicted by timelines 70 and 72 the synchronous task associated with sum block 46 performs multiple read operations (R1-R5) at time intervals 76, and the asynchronous task of algorithm block 44 performs multiple write operations (W1-W2) to memory at time intervals 74. Hence, because the asynchronous task associated with algorithm block 44 is assigned a higher priority than the synchronous task associated with sum block 46 the asynchronous task, when accessing the memory spaced shared by the tasks, preempts the synchronous task at time intervals 78 of timeline 72. As such, when the synchronous task of sum block 46 performs a first read (R1), from memory the asynchronous task associated with algorithm block 44 preempts the first read (R1) to update memory by carrying out a first portion of a write operation (W1) as depicted in timeline 70. As a result, the discrete task associated with sum block 46 continues or starts a second read (R2) upon completion of the first portion of a write operation (W1). Consequently, the read operation of the discrete task associated with the sum block 46 reads partially updated data and hence results in a corrupted data operation.
FIGS. 2 and 3 illustrate the lack of certainty regarding data integrity that can occur when transferring data between two tasks having different operating rate characteristics assigned different priorities. Although the lack of certainty regarding data integrity is described in context between a synchronous task and an asynchronous task, like difficulties apply in data transfer operations in a context between two synchronous tasks and in a context between two asynchronous tasks. To address the lack of certainty regarding data integrity in such data transfers, a number of data transfer mechanisms have been developed to provide an assurance of data integrity when transferring data between tasks having different operating rate characteristics and different priorities. One such data transfer mechanism uses a non-portable semaphore to control access to the memory space shared by the two tasks having the different operating rate characteristics and different priorities.
FIG. 4 depicts two timelines 80 and 82 representing use of a non-portable semaphore to control access to memory space shared between an asynchronous task and a synchronous task where the asynchronous task is assigned a lower priority than a synchronous task. For illustrative purposes timeline 80 represents an asynchronous task associated with algorithm block 44 and timeline 82 represents a synchronous task associated with sum block 46. As timeline 82 depicts, the synchronous task associated with sum block 46 performs a number of read operations (R1-R9) at time intervals 86. Timeline 80 depicts the asynchronous task associated with algorithm block 44 as performing a write operation at time interval 84 to the memory space shared with the synchronous task associated with sum block 46. As timelines 80 and 82 illustrate, the asynchronous task associated with algorithm block 44 is able to complete the write operation during time interval 84 without being preempted by the synchronous task associated with sum block 46. That is, read R5 of the synchronous task does not preempt the write operation of the asynchronous task, however, the execution of the higher priority synchronous task associated with sum block 46 is delayed as illustrated by time period 88. Although assurance of data integrity is accomplished through the use of a non-portable semaphore shared between the asynchronous task and the synchronous task, task preemption is disabled which can lead to further problems, such as delayed execution in a real time operating system.
Another known solution for ensuring data integrity when transferring data between blocks associated with tasks having different operating rate characteristics and different priorities is the use of writer block and reader block pairs. FIG. 5 illustrates such a known solution. Multi-rate graphical model 10A in addition to like blocks discussed above with reference to FIG. 1 includes algorithm block 44A. Algorithm block 44A includes a reader block 90B, an integration block 96, a gain block 98, a writer block 92A, and a writer block 94A. To address the issue of ensuring data integrity, multi-rate graphical model 10A includes a first writer/reader block pair in writer block 90A and reader block 90B, a second writer/reader block pair in writer block 92A and reader block 92B, and a third writer/reader block pair in writer block 94A and reader block 94B. This known solution employs writer/reader block pairs on each signal line in the multi-rate graphical model wherever a rate transition occurs.
For example, in multi-rate graphical model 10A a rate transition occurs between input nodes 38, 40, 42 and an input node of the integration block 96 and an input node of the gain block 98. Accordingly, a pair of writer/reader blocks such as, the pair defined by writer block 90A and reader block 90B is placed between the input nodes 38, 40, 42 and the input nodes of the integration block 96 and the gain block 98 to provide data integrity when transferring data between these nodes. Likewise, a rate transition occurs between an output node of the integration block 96 and third output node 52. As such, multi-rate graphical model 10A is configured to include a second writer/reader block pair formed by writer block 92A and reader block 92B. Similarly, a rate transition occurs between an output node of gain block 98 and an input node of sum block 46. As such, multi-rate graphical model 10A is configured to include a third writer/reader block pair formed by writer block 94A and reader block 94B.
Unfortunately, use of writer/reader block pairs requires disabling interrupts within the generated real-time application for example, first interrupt 26A and second interrupt 26B. Moreover, the writer/reader block pairs use a double buffering mechanism to transfer data between two portions of multi-rate graphical model 10A that execute with different rate characteristics and are therefore not well suited for use in a real time operating system.
Although a number of known techniques are available to provide data integrity when transferring data between tasks in a multi-rate graphical model having different operating rate characteristics and priorities, many of these known solutions are considered non-portable because they rely on supplier specific extensions to ANSI C, or disabling of interrupts. Furthermore, many of the known solutions require problematic and unnatural modeling constructs, such as the use and pairing of reader blocks and writer blocks. Moreover, the known solutions do not provide the ability for a user or creator of a multi-rate graphical model to selectively enable and disable data integrity to perform trade off studies between assurance of data integrity when transferring data between tasks in the model, and any resource overhead that such an assurance imposes, for example, memory overhead and throughput overhead. Accordingly, a need exists for a data transfer mechanism that overcomes such known problems.